module ysyx_22040213_signcompare (
	input [63:0]data1,
	input [63:0]data2,
	output reg compareflag
);
always @(data1 or data2)begin
	if(data1[63] == 1 && data2[63] == 0)
	compareflag = 0;
	else if(data1[63] == 0 && data2[63] == 1)
	compareflag = 1;
	else if(data1[63] == 1 && data2[63] == 1)
	  begin if(data1 > data2)
	  	compareflag = 0;
		else
		compareflag = 1;
	  end
	else begin if(data1 > data2)
	  	compareflag = 1;
		else
		compareflag = 0;
	 end
 end
 endmodule
	
